Multi-port random access memories (RAM) are substantially faster than standard RAM and commonly referred to as video random access memories (VRAM) because of their effectiveness in video systems. FIG. 1 illustrates a block diagram of a prior art multi-port memory similar to the memory described in U.S. Pat. No. 4,891,794 issued to Hush et al. entitled "Three Port Random Access Memory" assigned to the assignee of the present invention and incorporated by reference. In its simplest form, the multi-port memory includes a dynamic random access memory (DRAM) 90, a DRAM controller 92, two serial access memories (SAM) 94, 96 and a SAM controller 98. Each SAM is essentially a long shift register which can receive a block of data from the DRAM and serially shift the data out through a data port 99. The SAM can also serially shift data in through the serial port and transfer the data to the DRAM.
The DRAM is a dynamic array for storing multi-bit registers in multiple two dimensional planes each having memory cells arranged in rows and columns. The DRAM has address line inputs 95 and a plurality of input/output lines 97. Each of the registers are defined by the same row and column addresses in the multiple planes. Each SAM has a multi-bit register row associated with each of the planes of the DRAM were the columns of the DRAM correspond to the bits of the register row. In general, the DRAM and SAM's can operate either independently or in limited combinations for internal transfers of data. When operating in combination, the SAM's are structured to allow each SAM to access one row of the DRAM.
Various features have been incorporated in VRAM's to speed the transfer of data to and from an associated graphics processor or microprocessor. One example of a function used to speed memory writing is the `block write` function. U.S. Pat. No. 5,282,177 entitled "Multiple Register Block Write Method and Circuit for Video DRAMs" issued to McLaury on Jan. 25, 1994 describes several methods and circuits for block writing to a DRAM and is incorporated herein by reference.
The block write is useful in a VRAM to quickly clear a large area of frame buffer or to create a background for a display. The block write function simultaneously writes to a block of memory cells instead of writing to each cell individually. The block of cells can be pre-selected number of cells in a row of the DRAM or the entire row of memory cells. The block of selected cells in each plane of memory is written to the same state. That is, one bit of a multi-bit write register is written to each cell of the selected block.
U.S. Pat. No. 5,282,177 discloses a multiple register block write. The multiple register block write is similar to the block write described above except the write register has multiple registers. The multiple write register has a plurality of eight bit static memory registers. Any one of the plurality of write registers can transfer data to the VRAM. The multiple write register, therefore, eliminates the need to re-load a single write register for different block writes by pre-loading all of the multiple write registers.
The prior art allows for a block of memory to be written to by one bit of a write register. Each memory cell of the block is written to the same logic state, 1 or 0. Prior art fails to provide a means for transferring different logic states to the different cells of each row of the block via the random access port.
Block write functions allow for fast, efficient transfers of data to a memory, such that blocks of memory can be simultaneously written to a common state. If a portion of the block needs to be a different state, that portion must be either blocked from writing or edited by a later write function. Block writing to a block of memory followed by several edit operations is time consuming. What is needed is the ability to write a block of memory so that subsequent editing is reduced or eliminated.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a circuit and method for block writing data to a DRAM such that the individual cells of a selected block can be written to different states, in a simultaneous fashion.